There have been remarkable increases in capacity and speed of a memory system that uses semiconductor memory devices such as dynamic RAMs. In the memory system on which DDR SDRAMs (Double Data Rate Synchronous DRAMs) are mounted in particular, internal operations of the semiconductor memory devices are pipelined, and commands that have been supplied from an outside in synchronization with a clock are sequentially executed. Together with the sequential execution of the commands, it is arranged that data transfer is performed between a DDR SDRAM and the memory controller at a rate twice as the frequency of the clock, thereby implementing a high-speed system operation. In the DDR SDRAM or the like, a DLL (Delay Locked Loop) circuit is employed. Then, an internal circuit is operated in synchronization with the clock supplied from the outside. High-speed data transfer is thereby implemented. In the DDR SDRAM after a DDR2 in particular, a termination resistance is included in each of data input/output terminals such as a DQ terminal and a DQS terminal. Then, a control signal is supplied to an ODT terminal of the DDR SDRAM from the memory controller to control turning on or off of the termination resistance, thereby reducing reflection from the data input/output terminal. A high data transfer is thereby implemented.
FIG. 1 is a configuration diagram of an overall memory system of a related art. FIG. 1 is the memory system for reading and writing of 64 bits in parallel. A semiconductor memory device 101 is used for reading and writing of eight bits in parallel. Eight semiconductor memory devices 101 are connected in parallel to perform reading and writing of 64 bits in parallel. In the memory system in FIG. 1, a configuration is assumed in which two ranks of the semiconductor memory devices 101 are respectively mounted on two DIMMs (Dual Inline Memory Modules). That is, the memory system is formed of the semiconductor memory devices of a total of four ranks which are indicated by DIMM1 Rank-1, DIMM1 Rank-2, DIMM2 Rank-1, and DIMM2 Rank-2. Each rank is further formed of the eight semiconductor memory devices 101. A total of 4 ranks*8=32 semiconductor memory devices 101 are mounted. FIG. 1 illustrates only three of the eight semiconductor memory devices 101 connected in parallel. Signals that control these 32 semiconductor memory devices 101 are supplied from the memory controller 102, and data input/output is performed between the memory controller and each of the semiconductor memory devices 101.
Referring to FIG. 1, the memory controller 102 is directly connected to each semiconductor memory device 101. The memory system may include a so-called Registered DIMM or a Fully Buffered DIM (FBD1MM) in which a PLL or a buffer register is arranged between the memory controller 102 and the semiconductor memory device 101 for each DIMM, and timing synchronization with the memory controller is sought for each DIMM. The memory controller 102 may be an LSI having a function dedicated for memory control. Alternatively, a CPU may directly control the memory. Alternatively, the memory controller 102 may be formed of a plurality of LSIs.
Referring to FIG. 1, reference characters ADR and CMD respectively indicate an address signal and a command signal, which are connected in common to the semiconductor memory devices 101 of each rank, from the memory controller 102. The command signal CMD includes a row address strobe signal/RAS, a column address strobe signal/CAS, and a write enable signal/WE. Signals DQ0 to DQ63 are bidirectional data input/output signals used for transfer of read/write data or the like between the memory controller 102 and the semiconductor memory devices 101. It is assumed that each semiconductor memory device 101 is used for input/output of eight bits in parallel. Thus, the eight semiconductor memory devices 101 are connected in parallel in order to accommodate 64 bits of the signals DQ0 to DQ63. These data input/output signals DQ0 to DQ63 are also connected in common to each rank. DQS0 and /DQS0 signals, DQS1 and /DQS1 signals, DQS2 and /DQS2 signals, DQS3 and /DQS3 signals, DQS4 and /DQS4 signals, DQS5 and /DQS5 signals, DQS6 and /DQS6 signals, and DQS7 and /DQS7 signals are respectively differential data strobe signals. Each pair of the differential data strobe signals is transferred to a corresponding one of the semiconductor memory devices 101 from the memory controller 102 at a time of a write operation, and is transferred to the memory controller 102 from the corresponding one of the semiconductor memory devices 101 at a time of a read operation. These DQS and /DQS signals are bidirectional input/output signals. The data strobe DQS and /DQS signals output by the semiconductor memory device 101 at the time of the read operation are synchronized with a change point of read data. Thus, when the DQS and /DQS signals are used as the strobe signals on the side of the memory controller 102, the phases of the DQS and /DQS signals are deviated at a timing in which a data signal can be latched. These data strobe signals DQS0 to DQS7 and /DQS0 to /DQS7 are also connected in common to each rank of the semiconductor memory devices. However, an independent pair of the DQS and /DQS signals is connected to each of the eight semiconductor memory devices 101 of each rank connected in parallel.
Clock signals CK0 to CK3 and /CK0 to /CK3, clock enable signals CKE0 to CKE3, chip select signals /CS0 to /CS3, and embedded termination resistance control signals ODT0 to ODT3 are signals that are output from the memory controller 102 to the semiconductor memory devices 1. Different ones of these signals that are independent are output for each rank. The clock signals CK0 to CK3 and /CK0 to /CK3 are signals that are supplied to the semiconductor memory devices 1 as system clocks. A command for a read, a write, or the like supplied from the memory controller 102 to the semiconductor memory device 101 is supplied in synchronization with a corresponding pair of the system clocks. The clock enable signals CKE0 to CKE3 are signals each of which determines whether the corresponding clock CK is valid or invalid. When the clock enable signal CKE is high at a rising edge of the corresponding clock CK, the subsequent rising edge of the corresponding clock CK is valid. Edges of the corresponding clock CK other than the subsequent rising edge are invalid. When each of the chip select signals /CS0 to /CS3 is low, input of a command is valid. When each of the chip select signals /CS0 to /CS3 is high, the command is ignored. Operation, however, is continued. By supplying the command to the semiconductor memory device 101 of an arbitrary one of the ranks using this chip select signal, a selective access can be made. When values of termination resistances inside the respective memory devices 1 are not infinite, the embedded termination resistance control signals ODT0 to ODT3 can control turning on or off of the termination resistances. When the embedded termination resistance control signals ODT0 to ODT3 are high, the termination resistances are turned on. When the embedded termination resistance control signals ODT0 to ODT3 are low, the termination resistances are turned off.
With respect to routing of data buses (for the DQ signals, DQS signals) from the memory controller to the semiconductor memory devices 101 in FIG. 1, the routing is performed using a so-called fly-by (FLY-BY) topology. In this topology, the DIMM1s are mounted at far ends of lines extending from the memory controller 102 and the DIMM2s are mounted midway from the memory controller 102 to the DIMM1s so that no stub (stub, or unterminated section of line) occurs even when only the DIMM1s are mounted and no DIMM2s are mounted. Routing by the fly-by topology is to prevent signal reflection from the stub when only the DIMM1s are mounted without mounting the DIMM2s.
Next, an example of preferable setting of termination resistances when the semiconductor memory device 101 is a DDR3 SDRAM is shown in FIG. 2. FIG. 2 assumes a case (2R/2R) where DDR3 SDRAMs having two ranks of the DIMM1s and two ranks of the DIMM2s have been mounted, a case (2R/1R) where DDR3 SDRAMs having two ranks of the DIMM1s and one rank of the DIMM2 have been mounted, and a case (1R/1R) where DDR3 SDRAMs having one rank of the DIMM1 and one rank of the DIMM2 have been mounted. FIG. 2 shows each of write and read (WRITE, READ) commands supplied from the memory controller 102, the DIMM to be accessed by the write or read command and the rank of the DIMM, a termination resistance value of the memory controller 102 when the write or read command is executed, and a termination resistance value of each rank of each DIMM mounted on a board in each case. Termination resistance values are set in termination resistance value specifying registers of the semiconductor memory devices 101 by the memory controller 102 in advance.
The DDR3 SDRAM has a dynamic ODT function. Thus, the DDR3 SDRAM includes a write-command execution time termination resistance value specifying register and a nominal termination resistance value specifying register. The write-command execution time termination resistance specifying register specifies a termination resistance value when the write command is executed. The nominal termination resistance value specifying register specifies a termination resistance value except when the write command is executed. When the dynamic ODT function is selected, the termination resistance value can be changed between a time when the write command is executed and a time except when the write command is executed. That is, when the dynamic ODT function is used, whether to turn off or turn on the termination resistance is controlled by the ODT terminal. When the termination resistance is turned on, different resistance values of the termination resistance can be specified between the time when the write command is executed and the time except when the write command is executed. Referring to FIG. 2, different resistance values are set as the termination resistance value of the rank targeted for execution of the write command and the termination resistance value not targeted for execution of the write command, using the dynamic ODT function. When the termination resistance value setting as shown in FIG. 2 is performed, signal reflection can be appropriately prevented.
Specifications of the DDR3 SDRAM including the dynamic ODT function are described in Non-patent Document 1 (on pages 89 to 105). Patent Document 1 describes an example of termination resistance setting similar to that in FIG. 2.    [Patent Document 1] U.S. Pat. No. 7,342,411    [Non-patent Document 1] JEDEC STANDARD DDR3 SDRAM Specification, JESD79-3B, April, 2008, JEDEC Solid State Technology Association (JEDEC SOLID STATE TECHNOLOGY ASSOCIATION), pages 37, 89 to 105